Design and implementation of 16 X 16 Truncated multiplier with different families of Xilinx
نویسندگان
چکیده
Multiplication and Squaring functions are widely used in many real time applications. They form an integral part in implementation of many Digital Signal Processing, Digital Image Processing and Multimedia algorithms. The size and power consumption of a DSP chip is influenced by the multiplication and squaring architectures that are used. The aim of this paper is to propose a novel fixed width, 16 bit parallel array multiplier. The proposed approach is aimed at providing a degree of flexibility to designers when it comes to designing fixed width multipliers with reduced area and delay. The design being proposed was implemented in Verilog, and simulation were carried out in Xilinx version 13.2.
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